This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the subject matter described and/or claimed below. This discussion is believed to be helpful in providing background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, not as admissions of prior art.
Non-volatile solid-state read/write memory devices are commonplace in many modern electronic systems, particularly in portable electronic devices and systems. Conventional types of non-volatile solid-state memory devices include those referred to as electrically programmable read-only memory (EPROM) devices.
Modern EPROM memory cells include one or more “floating-gate” transistors that store the data state. In general, a floating gate transistor is based on conventional MOSFET transistors in structure, but includes an additional gate element that is electrically isolated, hence the term “floating gate.” This floating gate element functions as the storage element for the memory cell. Floating-gate transistors are “programmed” by the application of a bias that enables holes or electrons to tunnel or be injected through a thin dielectric film onto the electrically isolated floating gate. This trapped charge on the floating gate (e.g., a programmed state) will modulate the apparent threshold voltage of the memory cell transistor, as compared with the threshold voltage with no charge trapped on the floating gate (e.g., the un-programmed state). This difference in threshold voltage can be detected by sensing the resulting difference in source-drain conduction, under normal transistor bias conditions, between the programmed and un-programmed states.
Some EPROM devices are “erasable” in that the trapped charge can be removed from the floating gate, for example, by exposure of the memory cells to ultraviolet light (such memories referred to as “UV EPROM”) or by application of a particular electrical bias condition that enables tunneling of the charge from the floating gate (such memories referred to as electrically-erasable programmable read-only memory or EEPROM). “Flash” memory devices are typically realized by EEPROM memory arrays in which the erase operation is applied simultaneously to a “block” of memory cells. One class of EPROM memory is referred to as “one-time programmable” (OTP) memory. OTP memory may be constructed similarly or identically to UV EPROM cells, and as such are not electrically erasable. When mounted in an opaque package that prevents the OTP cells from being exposed to ultraviolet light, these memory cells cannot be erased once programmed, hence the term OTP.
The convenience and efficiency of modern EPROM functions has made it commonplace to embed non-volatile memory arrays within larger scale integrated circuits, such as modern complex microprocessors, digital signal processors, and other large-scale logic circuitry. Such embedded non-volatile memories can be used as non-volatile program memory storing software routines executable by the processor, and also as non-volatile data storage. On a smaller scale, non-volatile memory cells can realize control registers by way of which a larger scale logic circuit can be configured, or can be used to trim analog levels after electrical measurement. In embedded applications, OTP memories are useful for storing the program code to be executed by the embedding microcontroller or microprocessor.
As stated above, non-volatile memory, such as EPROM and OTP devices, may be constructed based on floating gate transistors, which typically use a conventional MOSFET transistor structure with the addition of a floating gate element. For example, a floating gate transistor based on a p-type MOSFET (PMOS) is commonly used in constructing such devices. This is at least due in part to PMOS transistors being formed in an n-well structure when the underlying substrate is a p-type substrate, which provides better substrate isolation and less leakage. In some EPROM and OTP devices, the PMOS transistor defining a memory cell can be constructed with a buried channel region, which can favorably result in lower noise and higher drive current. However, buried channel devices often have a lower threshold voltage due to the implantation of the buried channel region. This can result in a fairly high off state current (I-off) compared to the on current (I-on), which can result not only in higher current leakage but also reduce the operating margin and lifetime of the memory cell.
Existing approaches for addressing the high leakage problem sometimes associated with buried channel devices aim to increase the on-to-off current ratio (I-on/I-off). One such approach is to increase the channel length of the device. However, this increases the overall area of the memory cell, which can be undesirable as the demand for memories with higher bit density continues to grow. The on-to-off current ratio can also be increased by either increasing the programmed state current (I-on) of the memory cell or decreasing the off state current (I-off). However, increasing the programmed state current can also result in an increase in programming voltage and programming time, which is also undesirable. Accordingly, semiconductor circuit designers and manufacturers are continually seeking techniques to reduce the off current of such memory cells to improve performance and reliability.